Modern Processor Design Fundamentals Of Superscalar Processors Pdf
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Typically, the number of instructions that can fit into an instruction window is less than the total number of instructions that are issued from the front-end of a processor. This means that some instructions will have to be delayed for a while before they can be dispatched to a functional unit. If the number of instructions that can fit into the instruction window is large, the delay could lead to a situation where instructions could not be issued fast enough to keep the front-end of the processor operating at its maximum rate. The situation is best illustrated in a case where the number of instructions that can fit into the instruction window is one, and that one instruction is a load instruction.
Suppose that the load instruction is a load queue (LQ) instruction that loads the data from the register R1 into the register R2, and that the next instruction is an add instruction for which the addend is a constant and the addend is also in the register R2. If the load queue instruction is issued from the front-end of the processor before the next instruction is issued, the resulting situation is illustrated in Figure 1. The load queue instruction may be held in the instruction window for some time, and then will be dispatched to the load queue (LQ) when the add instruction is not issued yet. Meanwhile, the add instruction will reach the execution stage and will perform a constant addition. If the load queue instruction is dispatched to the load queue (LQ), the data from R1 will be loaded into R2, and R2 would be updated. The problem with this simple example is that it will lead to an internal deadlock, because the load queue instruction will not be able to issue from the load queue (LQ) until the add instruction is finished.
We assume that all registers are 32-bit, although in most MIPS designs, a 16-bit register (such as the X register) is used. (The X, Y, and Z registers are, of course, also 16-bit, but the Y and Z registers are used to hold the addresses of the instructions, so they are effectively the control registers.)
In later chapters, we will look at the design of each instruction pipeline in more detail. Theprocessor will be able to execute multiple instructions per cycle if each instruction isexecuted as the previous instruction is being retired. In this chapter, however, we will only consider instruction latencies, since we will only execute one instruction per cycle.
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